Job Description

JOB DESCRIPTION:

Ø  Responsible for all aspects of physical design and implementation. Responsibilities include chip floor plan, power / clock distribution, chip assembly and P&R, timing closure, power and noise analysis and back-end verification across multiple projects.

Ø  High level of expertise in complete physical implementation tool chain; Good working knowledge and experience of netlist to GDSII flows Hands-on technical experience with deep sub-micron technology ASIC design, STA and physical implementation;

Ø  Expertise in Synthesis, Static Timing Analysis and Timing Closure of High Performance Hard-Macros and/or Full Chip Physical Designs

Ø  Should be independent, self-driven and a strong team player.

Ø  Thorough understanding and knowledge of the entire Back end flow Netlist to gdsii

Ø  Must be familiar with Industry standard tools like ICC / Encounter / Talus / Olympus

Ø  Should have expertise in Timing analysis and closure

Ø  Should have Tcl and perl scripting skills

Ø  Should have work experience in the latest technology nodes like 16nm/14nm

Ø  Should be familiar with low-power design and their impact on Back end flow (power switches / Level shifter / Isolation cell / retention cells / Back biasing / Forward biasing